URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] - Rev 333

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Rev	Log message	Author	Age	Path
333	update TODO	hellwig	2785d 00h	/
332	update COPYING	hellwig	2846d 00h	/
331	machine monitor: init kbd and dsp only if explicitly requested	hellwig	2846d 14h	/
330	sim/getline/testgl.c: return type of main() changed to int	hellwig	2846d 14h	/
329	lcc/lburg/gram.y: prototype for yylex() added	hellwig	2846d 15h	/
328	lcc/etc/lcc.c: return type of main() changed to int	hellwig	2846d 15h	/
327	flag -m32 in compilation of vcdchk deleted	hellwig	3114d 01h	/
326	RAM simulation access times set to realistic values	hellwig	3224d 19h	/
325	memory speed measurement for new controller added	hellwig	3233d 10h	/
324	README updated	hellwig	3233d 11h	/
323	memspeed renamed to memspeed-1	hellwig	3233d 11h	/
322	README updated, Makefile added	hellwig	3233d 23h	/
321	README updated	hellwig	3234d 00h	/
320	README updated	hellwig	3234d 20h	/
319	memory controller 2, FPGA realization	hellwig	3235d 00h	/
318	memory controller 1, FPGA realization	hellwig	3235d 00h	/
317	README updated	hellwig	3235d 15h	/
316	README added	hellwig	3235d 19h	/
315	README added	hellwig	3235d 19h	/
314	memory controller simulation 2	hellwig	3235d 21h	/
313	memory controller simulation 1	hellwig	3235d 22h	/
312	memory controller simulation 0	hellwig	3235d 23h	/
311	README updated	hellwig	3236d 01h	/
310	verilated mc implementation with and without trace	hellwig	3236d 21h	/
309	multicycle simulation of ECO32, using Verilator	hellwig	3237d 21h	/
308	multicycle design, suitable for being verilated	hellwig	3238d 01h	/
307	several tests got duration.dat files	hellwig	3238d 15h	/
306	tool to show display output added	hellwig	3238d 22h	/
305	tool to show serial output added	hellwig	3238d 23h	/
304	Makefile updated	hellwig	3241d 10h	/

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Subversion Repositories eco32

[/] - Rev 333

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