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248 wb_rst_i is used for MIIM reset. mohor 7865d 21h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7869d 00h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7869d 00h /
245 Rev 1.7. mohor 7869d 18h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7869d 20h /
243 Late collision is not reported any more. tadejm 7870d 02h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7870d 16h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7870d 16h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7870d 16h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7870d 16h /
238 Defines fixed to use generic RAM by default. mohor 7882d 20h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7885d 02h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7885d 02h /
235 rev 4. mohor 7885d 16h /
234 Figure list assed to the revision 3. mohor 7886d 01h /
233 Revision 0.3 released. Some figures added. mohor 7886d 01h /
232 fpga define added. mohor 7890d 20h /
231 Description of Core Modules added (figure). mohor 7892d 21h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7896d 18h /
229 case changed to casex. mohor 7896d 18h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7896d 22h /
227 Changed BIST scan signals. tadejm 7896d 22h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7896d 23h /
225 Some minor changes. tadejm 7896d 23h /
224 Signals for a wave window in Modelsim. tadejm 7897d 01h /
223 Some code changed due to bug fixes. tadejm 7897d 01h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7900d 23h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7900d 23h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7903d 23h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7903d 23h /

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