Rev |
Log message |
Author |
Age |
Path |
44 |
Changed design for Kintex 7 based boards (AFCK, KC705) so that
they use the VEXTPROJ environment for VCS friendly project management
(described in http://doi.org/10.1117/12.2247944 ) |
wzab |
2781d 08h |
/ |
43 |
Removed latch on "dbg" signal |
wzab |
2781d 08h |
/ |
42 |
KC705 design upgraded to Vivado 2016.4
Corrrected indentation in a few files in AFCK design |
wzab |
2781d 12h |
/ |
41 |
The AFCK project upgraded to Vivado 2016.4 |
wzab |
2781d 13h |
/ |
40 |
The "jumbo frame version" renamed from "experimental" to "stable". |
wzab |
2781d 18h |
/ |
39 |
Added receiver2t4 - program allowing to receive data from 4 links simultaneously |
wzab |
3350d 07h |
/ |
38 |
In synthesis scripts added waiting, until bitsream is generated... |
wzab |
3381d 16h |
/ |
37 |
Added new design for AFCK board, which uses 8 10 Gbps links.
Additionally added I2C control of the AFCK Si57x based clock.
The I2C controller is driven via VIO blocks controlled by JTAG
interface from Vivado Tcl console.
Tcl scripts are in the fpga/src/AFCK/i2c_tools directory.
To configure clock to 156.25MHz, and to route it to links,
change directory to fpga/src/AFCK/i2c_tools and do
"source start_10g_links.tcl".
After the clock is reprogrammed, reconfigure the FPGA again
(it seems, that there is a problem with reseting links after
clock is reconfigured). |
wzab |
3383d 07h |
/ |
36 |
Added signals needed to ensure, that Si570/1 chip generates the clock.
Added signals driving the rate select lines in the SFP+ modules high.
Added two XDC files - the first one for FM-S14 in the FMC1
connector, the second one for FM-S14 in the FMC2 connector. |
wzab |
3399d 09h |
/ |
35 |
Changed comment in definition of the descriptor record
Updated IP cores in project for KC705 (to Vivado 2014.4) |
wzab |
3502d 09h |
/ |
34 |
The "old stable" version moved to separate directory. |
wzab |
3516d 14h |
/ |
33 |
Added script for automatic compilation of FADE for AFCK, using Vivado 2014.4 |
wzab |
3518d 19h |
/ |
32 |
Added the 4-channel FADE test implementation for the AFCK board. |
wzab |
3518d 23h |
/ |
31 |
Added receiver2t_cmd to the Makefile |
wzab |
3523d 12h |
/ |
30 |
Corrected error which slows down handling of user commands (the thread
executing the user command used wait_event_timeout instead of
wait_event_timeout_interruptiple).
Added demo program which tests time of execution of the user's
command. |
wzab |
3523d 13h |
/ |
29 |
Fixed two mistakes in mutex management (mutex not unlocked, when function leaved after an error)
Fixed dead URL in comments. |
wzab |
3528d 14h |
/ |
28 |
Correction of an obvious mistake in the Linux driver, which lead to deadlock
when two applications (or two threads) tried to open the same FADE device. |
wzab |
3532d 12h |
/ |
27 |
Added file fade_one_channel, allowing to implement multiple FADE instances in a single FPGA. |
wzab |
3546d 21h |
/ |
26 |
Corrected small bug in CRC update in eth_sender8,vhd
Added counter of retransmitted packets.
Some minor changes in delay update parameters. |
wzab |
3581d 07h |
/ |
25 |
Modified the Tcl script for KC705 so, that it automatically runs synthesis, implementation and generates bitstream. |
wzab |
3604d 22h |
/ |
24 |
Added build scripts for KC705 (somehow they got omitted in version 22) |
wzab |
3605d 11h |
/ |
23 |
Added script allowing for batch compilation of FADE 10G for Atlys.
Just run build_proj_atlys.sh
Removed compilation of receiver2.c (which has been deleted) in the Makefile.
Slightly changed order of operation in the receiver2t.c |
wzab |
3605d 11h |
/ |
22 |
Sources reorganized so, that each ".xci" is in a separate directory.
Added script for rebuilding of Vivado project for KC705.
Just run the build_proj_kc705 script, and the project
will be created as kc705_10g3.xpr in the kc705_10g3 drirectory.
You can open it later on in Vivado 2014.3 and build the bitstream. |
wzab |
3605d 12h |
/ |
21 |
Changed the top entity for KC705, so that the FADE core is correctly reset
by the RESETMAC command.
Changed sending of the FCMD_RESET command form driver to the FPGA (as it
is not confirmed - the reinitialized core can't confirm the command).
Changed the receiver2t demo program so that it sends RESETMAC three times
before the transmission is started.
In the future, probably there should be a STATUS ioctl, which would
verify, that the core has been reset by RESETMAC.
Then the program should send RESETMAC, and afterwards read the STATUS,
verifying, that RESETMAC arrived FPGA. If not it should repeat the
above procedure (not implemented yet). |
wzab |
3605d 18h |
/ |
20 |
Cured problem with dta_eod missed, when buffer was full at the moment
when dta_eod was asserted.
It caused the client program to hang, as no end of data was transmitted
and no new data arrived... |
wzab |
3606d 10h |
/ |
19 |
The send_cmd function protected to attempt to call it if the Ethernet device was not
claimed before (previously it caused a problem with NULL pointer dereference
in the ioctl in kernel code).
Moved the Ethernet device name to a macro, so it is easier to modify it, when
someone tests in different machines (e.g. the 10Gb/s NIC for tests with
KC705 is p4p1, while 1Gb/s NIC for tests with Atlys is eth0) |
wzab |
3606d 11h |
/ |
18 |
Changed handling of commands so, that all commands are now confirmed - even start and stop
(which previously were not confirmed - successful reception of start was confirmed
by sending of data packets (what if there was no data at the moment?), successful
reception of stop was confirmed by end of data stream).
Added also flushing of data stream after reception of stop command.
The receiver2t.c implements suggested method of communication with the FADE driver.
One thread is responsible for reception and processing of data, while another thread
is responsible for sending of control commands. |
wzab |
3607d 07h |
/ |
17 |
Corrected mutex management in ioctl. |
wzab |
3613d 11h |
/ |
16 |
Introduced inline functions simplifying reading and writing of packets' contents. |
wzab |
3613d 12h |
/ |
15 |
The previous experimental implemenation for 10Gb/s links has been replaced with the
new, rewritten implementation, which uses sequential numbering of packets instaed
of "sets of packets". This allowed to simplify the driver, and improve its performance.
Additionally a possibility to send user defined commands to the FPGA was added. |
wzab |
3621d 10h |
/ |