URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 22

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Rev	Log message	Author	Age	Path
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8049d 12h	/
21	no message	rherveille	8135d 13h	/
20	Added Appendix A	rherveille	8135d 13h	/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8139d 10h	/
18	no message	rherveille	8166d 05h	/
17	C-include file. Initial release	rherveille	8254d 10h	/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8266d 09h	/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8271d 08h	/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8271d 08h	/
13	Fixed some synthesis warnings.	rherveille	8282d 12h	/
12	no message	rherveille	8288d 04h	/
11	Changed RST_LVL define to parameter.	rherveille	8291d 11h	/
10	Created new directory structure. Added Verilog version.	rherveille	8313d 08h	/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8383d 03h	/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8383d 03h	/
7	added some remarks, fixed some sensitivity lists	rherveille	8452d 05h	/
6	fixed typo txt -> txr	rherveille	8456d 09h	/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8463d 07h	/
4	WISHBONE I2C Master Core: initial release	rherveille	8515d 10h	/
3	This commit was manufactured by cvs2svn to create tag 'first'.		8577d 10h	/
2	initial release	rherveille	8577d 10h	/
1	Standard project directories initialized by cvs2svn.		8577d 10h	/

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[/] - Rev 22

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