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Rev Log message Author Age Path
27 Cleaned up code rherveille 7862d 00h /
26 *** empty log message *** rherveille 7865d 08h /
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7893d 04h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7893d 04h /
23 *** empty log message *** rherveille 8020d 10h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8030d 15h /
21 no message rherveille 8116d 16h /
20 Added Appendix A rherveille 8116d 16h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8120d 12h /
18 no message rherveille 8147d 08h /
17 C-include file.
Initial release		 rherveille 8235d 13h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8247d 12h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8252d 11h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8252d 11h /
13 Fixed some synthesis warnings. rherveille 8263d 15h /
12 no message rherveille 8269d 06h /
11 Changed RST_LVL define to parameter. rherveille 8272d 14h /
10 Created new directory structure.
Added Verilog version.		 rherveille 8294d 10h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8364d 05h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8364d 05h /
7 added some remarks, fixed some sensitivity lists rherveille 8433d 08h /
6 fixed typo txt -> txr rherveille 8437d 12h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8444d 10h /
4 WISHBONE I2C Master Core: initial release rherveille 8496d 13h /
3 This commit was manufactured by cvs2svn to create tag 'first'. 8558d 12h /
2 initial release rherveille 8558d 12h /
1 Standard project directories initialized by cvs2svn. 8558d 12h /

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