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Rev Log message Author Age Path
33 Fixed a bug in the Command Register declaration. rherveille 7871d 03h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7881d 02h /
31 Core is now a Multimaster I2C controller. rherveille 7885d 03h /
30 Small code simplifications rherveille 7885d 03h /
29 Core is now a Multimaster I2C controller rherveille 7885d 04h /
28 *** empty log message *** rherveille 7910d 21h /
27 Cleaned up code rherveille 7910d 21h /
26 *** empty log message *** rherveille 7914d 05h /
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7942d 01h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7942d 01h /
23 *** empty log message *** rherveille 8069d 07h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8079d 12h /
21 no message rherveille 8165d 12h /
20 Added Appendix A rherveille 8165d 12h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8169d 09h /
18 no message rherveille 8196d 05h /
17 C-include file.
Initial release		 rherveille 8284d 09h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8296d 09h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8301d 07h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8301d 07h /
13 Fixed some synthesis warnings. rherveille 8312d 11h /
12 no message rherveille 8318d 03h /
11 Changed RST_LVL define to parameter. rherveille 8321d 10h /
10 Created new directory structure.
Added Verilog version.		 rherveille 8343d 07h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8413d 02h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8413d 02h /
7 added some remarks, fixed some sensitivity lists rherveille 8482d 05h /
6 fixed typo txt -> txr rherveille 8486d 09h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8493d 07h /
4 WISHBONE I2C Master Core: initial release rherveille 8545d 10h /

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