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Rev Log message Author Age Path
45 Added slave address configurability rherveille 7494d 15h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7579d 17h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7579d 17h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7589d 15h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7589d 15h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7589d 15h /
39 Forgot an 'end if' :-/ rherveille 7609d 11h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7612d 19h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7649d 10h /
36 Fixed cmd_ack generation item (no bug). rherveille 7764d 11h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7798d 02h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7802d 00h /
33 Fixed a bug in the Command Register declaration. rherveille 7824d 09h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7834d 09h /
31 Core is now a Multimaster I2C controller. rherveille 7838d 10h /
30 Small code simplifications rherveille 7838d 10h /
29 Core is now a Multimaster I2C controller rherveille 7838d 11h /
28 *** empty log message *** rherveille 7864d 03h /
27 Cleaned up code rherveille 7864d 03h /
26 *** empty log message *** rherveille 7867d 11h /
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7895d 08h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7895d 08h /
23 *** empty log message *** rherveille 8022d 13h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8032d 18h /
21 no message rherveille 8118d 19h /
20 Added Appendix A rherveille 8118d 19h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8122d 15h /
18 no message rherveille 8149d 11h /
17 C-include file.
Initial release		 rherveille 8237d 16h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8249d 15h /

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