OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 46

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
46 Fixed slave address MSB='1' bug rherveille 7523d 05h /
45 Added slave address configurability rherveille 7523d 05h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7608d 08h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7608d 08h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7618d 06h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7618d 06h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7618d 06h /
39 Forgot an 'end if' :-/ rherveille 7638d 02h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7641d 09h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7678d 01h /
36 Fixed cmd_ack generation item (no bug). rherveille 7793d 02h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7826d 16h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7830d 14h /
33 Fixed a bug in the Command Register declaration. rherveille 7853d 00h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7862d 23h /
31 Core is now a Multimaster I2C controller. rherveille 7867d 00h /
30 Small code simplifications rherveille 7867d 00h /
29 Core is now a Multimaster I2C controller rherveille 7867d 01h /
28 *** empty log message *** rherveille 7892d 18h /
27 Cleaned up code rherveille 7892d 18h /
26 *** empty log message *** rherveille 7896d 02h /
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7923d 22h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7923d 22h /
23 *** empty log message *** rherveille 8051d 04h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8061d 09h /
21 no message rherveille 8147d 10h /
20 Added Appendix A rherveille 8147d 10h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8151d 06h /
18 no message rherveille 8178d 02h /
17 C-include file.
Initial release		 rherveille 8266d 06h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.