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[/] - Rev 57

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Rev Log message Author Age Path
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6487d 07h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 7040d 05h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7041d 07h /
54 Fixed scl, sda delay. rherveille 7041d 07h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7337d 04h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7337d 05h /
51 Fixed simulation issue when writing to CR register rherveille 7391d 06h /
50 *** empty log message *** rherveille 7406d 00h /
49 Added testbench rherveille 7406d 01h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7407d 08h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7416d 04h /
46 Fixed slave address MSB='1' bug rherveille 7491d 05h /
45 Added slave address configurability rherveille 7491d 05h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7576d 08h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7576d 08h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7586d 06h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7586d 06h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7586d 06h /
39 Forgot an 'end if' :-/ rherveille 7606d 01h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7609d 09h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7646d 01h /
36 Fixed cmd_ack generation item (no bug). rherveille 7761d 02h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7794d 16h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7798d 14h /
33 Fixed a bug in the Command Register declaration. rherveille 7820d 23h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7830d 23h /
31 Core is now a Multimaster I2C controller. rherveille 7835d 00h /
30 Small code simplifications rherveille 7835d 00h /
29 Core is now a Multimaster I2C controller rherveille 7835d 01h /
28 *** empty log message *** rherveille 7860d 18h /

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