Rev |
Log message |
Author |
Age |
Path |
51 |
true dual port ram for xilinx |
JonasDC |
4142d 22h |
/ |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4142d 22h |
/ |
49 |
First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives. |
JonasDC |
4154d 17h |
/ |
48 |
Tag of the starting version of the project |
JonasDC |
4154d 17h |
/ |
47 |
added documentation for the IP core. |
JonasDC |
4222d 21h |
/ |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4222d 22h |
/ |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4222d 22h |
/ |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4226d 15h |
/ |
43 |
made the core parameters generics |
JonasDC |
4226d 15h |
/ |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4232d 23h |
/ |
41 |
removed deprecated files from version control |
JonasDC |
4232d 23h |
/ |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4241d 03h |
/ |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4241d 14h |
/ |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4241d 20h |
/ |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4245d 17h |
/ |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4246d 13h |
/ |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4246d 15h |
/ |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4246d 17h |
/ |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4246d 19h |
/ |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4246d 20h |
/ |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4247d 02h |
/ |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4247d 02h |
/ |
29 |
added software for generation of test input for the tesbenches |
JonasDC |
4247d 15h |
/ |
28 |
updated makefile for new pipeline sources |
JonasDC |
4247d 16h |
/ |
27 |
test input values for multiplier_tb |
JonasDC |
4247d 16h |
/ |
26 |
testbench for only the montgommery multiplier |
JonasDC |
4247d 16h |
/ |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4247d 16h |
/ |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4251d 01h |
/ |
23 |
added descriptive comments |
JonasDC |
4251d 02h |
/ |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4253d 20h |
/ |