Rev |
Log message |
Author |
Age |
Path |
64 |
added synthesis reports of xilinx and altera |
JonasDC |
4119d 17h |
/ |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4119d 17h |
/ |
62 |
not used anymore |
JonasDC |
4119d 20h |
/ |
61 |
updated comments, added optional altera constraint |
JonasDC |
4119d 20h |
/ |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4122d 10h |
/ |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4122d 11h |
/ |
58 |
made fifo full a warning |
JonasDC |
4125d 11h |
/ |
57 |
new fifo design, is now generic (verified with altera and xilinx) and uses block ram |
JonasDC |
4125d 11h |
/ |
56 |
this is a branch to test performance of a new style of ram |
JonasDC |
4125d 14h |
/ |
55 |
updated resource usage in comments |
JonasDC |
4126d 10h |
/ |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4126d 10h |
/ |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4126d 17h |
/ |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4126d 18h |
/ |
51 |
true dual port ram for xilinx |
JonasDC |
4126d 18h |
/ |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4126d 18h |
/ |
49 |
First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives. |
JonasDC |
4138d 13h |
/ |
48 |
Tag of the starting version of the project |
JonasDC |
4138d 13h |
/ |
47 |
added documentation for the IP core. |
JonasDC |
4206d 18h |
/ |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4206d 18h |
/ |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4206d 18h |
/ |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4210d 12h |
/ |
43 |
made the core parameters generics |
JonasDC |
4210d 12h |
/ |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4216d 19h |
/ |
41 |
removed deprecated files from version control |
JonasDC |
4216d 20h |
/ |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4225d 00h |
/ |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4225d 11h |
/ |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4225d 16h |
/ |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4229d 13h |
/ |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4230d 09h |
/ |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4230d 12h |
/ |