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[/] - Rev 79

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Rev	Log message	Author	Age	Path
79	Tag for version 1.3 (with new ram style	JonasDC	4167d 18h	/
78	updated documentation with new RAM style information	JonasDC	4167d 18h	/
77	found fault in code, now synthesizes normally	JonasDC	4173d 15h	/
76	testbench update	JonasDC	4176d 02h	/
75	made rw_address a vector of a fixed width	JonasDC	4176d 02h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4178d 22h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4179d 21h	/
72	deleted old resources	JonasDC	4180d 22h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4180d 22h	/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4180d 22h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4180d 22h	/
68	branch no longer needed	JonasDC	4181d 00h	/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4181d 01h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4181d 01h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4188d 17h	/
64	added synthesis reports of xilinx and altera	JonasDC	4188d 22h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4188d 22h	/
62	not used anymore	JonasDC	4189d 01h	/
61	updated comments, added optional altera constraint	JonasDC	4189d 01h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4191d 15h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4191d 16h	/
58	made fifo full a warning	JonasDC	4194d 16h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4194d 16h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4194d 19h	/
55	updated resource usage in comments	JonasDC	4195d 15h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4195d 15h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4195d 22h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4195d 22h	/
51	true dual port ram for xilinx	JonasDC	4195d 23h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4195d 23h	/

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[/] - Rev 79

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