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Rev	Log message	Author	Age	Path
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3986d 03h	/
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4050d 01h	/
88	small update on documentation, changed fault in axi control_reg	JonasDC	4056d 02h	/
87	updated documentation to version 1.4 core now supports the AXI4-Lite bus	JonasDC	4056d 02h	/
86	update on previous	JonasDC	4056d 02h	/
85	changed so that reset now also affects slave register	JonasDC	4056d 02h	/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4057d 11h	/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4059d 12h	/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4076d 08h	/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4076d 08h	/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4086d 02h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4086d 02h	/
78	updated documentation with new RAM style information	JonasDC	4086d 02h	/
77	found fault in code, now synthesizes normally	JonasDC	4091d 23h	/
76	testbench update	JonasDC	4094d 10h	/
75	made rw_address a vector of a fixed width	JonasDC	4094d 10h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4097d 06h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4098d 06h	/
72	deleted old resources	JonasDC	4099d 06h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4099d 06h	/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4099d 06h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4099d 06h	/
68	branch no longer needed	JonasDC	4099d 08h	/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4099d 09h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4099d 09h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4107d 01h	/
64	added synthesis reports of xilinx and altera	JonasDC	4107d 06h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4107d 06h	/
62	not used anymore	JonasDC	4107d 09h	/
61	updated comments, added optional altera constraint	JonasDC	4107d 09h	/

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[/] - Rev 90

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