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Rev	Log message	Author	Age	Path
23	better - root cause of synth issues was switch de-bounce. Working through remaining tests	stvhawes	3286d 13h	/
22	mixed rising_edge / falling_edge logic removed	stvhawes	3292d 05h	/
21	flakey sim bugs (1/10 test 2 fails)	stvhawes	3292d 07h	/
20	search_control_sim prepped	stvhawes	3299d 02h	/
19	search_control is up for simulation (ghdl) - tidied extra testbenches	stvhawes	3306d 02h	/
18	search_control is up for simulation (ghdl)	stvhawes	3306d 02h	/
17	persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id	stvhawes	3311d 13h	/
16	minor fixes to search_control test bench	stvhawes	3317d 23h	/
15	adding in search_control and testbench	stvhawes	3319d 04h	/
14	search_item_wrapper bench debugged	stvhawes	3325d 00h	/
13	test bench for search_item	stvhawes	3328d 04h	/
12	wrapper test for search_item	stvhawes	3333d 14h	/
11	multiplex searh item added	stvhawes	3334d 07h	/
10	split source files to sime and rtl	stvhawes	3348d 05h	/
9	highlevel block diagram added	stvhawes	3349d 02h	/
8	sim sequence error fixed, so 20% success -> 100% success for unit test on fpga	stvhawes	3349d 04h	/
7	split clock/byte_ready and fix logic	stvhawes	3353d 22h	/
6	fixing synthesizable	stvhawes	3355d 06h	/
5	fixing synthesizable	stvhawes	3355d 11h	/
4	developing ideas around unit test / fpga verification	stvhawes	3355d 23h	/
3	developing ideas around unit test / fpga verification	stvhawes	3355d 23h	/
2	initial sources, wrappers for regression test harness	stvhawes	3367d 01h	/
1	The project and the structure was created	root	3368d 20h	/

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