Rev |
Log message |
Author |
Age |
Path |
79 |
Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board |
julius |
5239d 14h |
/ |
78 |
Fixed typo in Silos workaround script |
rherveille |
5240d 09h |
/ |
77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5240d 10h |
/ |
76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5241d 09h |
/ |
75 |
Fixed toolchain script's cygwin ncurses check |
julius |
5246d 12h |
/ |
74 |
Toolchain script fix for ncurses header checking |
julius |
5264d 14h |
/ |
73 |
toolchain script error fix |
julius |
5264d 15h |
/ |
72 |
Toolchain install script: or1ksim location changed, few tweaks |
julius |
5267d 12h |
/ |
71 |
ORPSoC board builds, adding readmes |
julius |
5283d 19h |
/ |
70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5288d 00h |
/ |
69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5288d 01h |
/ |
68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5290d 16h |
/ |
67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5290d 19h |
/ |
66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5310d 17h |
/ |
65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5314d 23h |
/ |
64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5317d 18h |
/ |
63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5327d 15h |
/ |
62 |
This material is part of the separate website downloads directory. |
jeremybennett |
5338d 19h |
/ |
61 |
The build directory should not be part of the SVN configuration. |
jeremybennett |
5338d 19h |
/ |
60 |
Mark Jarvin's patches to support Mac OS X (Snow Leopard). |
jeremybennett |
5345d 12h |
/ |
59 |
Toolchain install script gcc patch change and gdb configure change |
julius |
5366d 13h |
/ |
58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5369d 11h |
/ |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5374d 15h |
/ |
56 |
adding generic pll model to orpsoc |
julius |
5382d 17h |
/ |
55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5385d 08h |
/ |
54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5395d 15h |
/ |
53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5413d 15h |
/ |
52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5414d 11h |
/ |
51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5428d 14h |
/ |
50 |
Adding or32_funcs.S |
julius |
5428d 18h |
/ |