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Rev Log message Author Age Path
1002 Now every ramdisk image should have init program. simons 7994d 05h /
1001 fixed load/store state machine verilog generation errors markom 7994d 05h /
1000 IC/DC cache enable routines fixed. simons 7994d 06h /
999 Now every ramdisk image should have init program. simons 7994d 07h /
998 added missing fout initialization markom 7994d 08h /
997 PRINTF should be used instead of printf; command redirection repaired markom 7994d 09h /
996 some minor bugs fixed markom 7995d 08h /
995 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7995d 16h /
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7995d 16h /
993 Fixed IMMU bug. lampret 7995d 16h /
992 A bug when cache enabled and bus error comes fixed. simons 7996d 01h /
991 Different memory controller. simons 7996d 01h /
990 Test is now complete. simons 7996d 01h /
989 c++ is making problems so, for now, it is excluded. simons 7997d 09h /
988 ORP architecture supported. simons 7998d 00h /
987 ORP architecture supported. simons 7998d 08h /
986 outputs out of function are not registered anymore markom 7998d 08h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7998d 20h /
984 Disable SB until it is tested lampret 7998d 20h /
983 First checkin lampret 7998d 22h /
982 Moved to sim/bin lampret 7998d 22h /
981 First checkin. lampret 7998d 22h /
980 Removed sim.tcl that shouldn't be here. lampret 7998d 22h /
979 Removed old test case binaries. lampret 7998d 22h /
978 Added variable delay for SRAM. lampret 7998d 22h /
977 Added store buffer. lampret 7998d 22h /
976 Added store buffer lampret 7998d 22h /
975 First checkin lampret 7998d 22h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7999d 00h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8001d 04h /

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