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Rev Log message Author Age Path
1003 cuc temporary files are deleted upon exiting markom 8013d 03h /
1002 Now every ramdisk image should have init program. simons 8013d 03h /
1001 fixed load/store state machine verilog generation errors markom 8013d 03h /
1000 IC/DC cache enable routines fixed. simons 8013d 04h /
999 Now every ramdisk image should have init program. simons 8013d 05h /
998 added missing fout initialization markom 8013d 06h /
997 PRINTF should be used instead of printf; command redirection repaired markom 8013d 07h /
996 some minor bugs fixed markom 8014d 06h /
995 This commit was manufactured by cvs2svn to create tag 'rel_3'. 8014d 14h /
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8014d 14h /
993 Fixed IMMU bug. lampret 8014d 14h /
992 A bug when cache enabled and bus error comes fixed. simons 8014d 23h /
991 Different memory controller. simons 8014d 23h /
990 Test is now complete. simons 8014d 23h /
989 c++ is making problems so, for now, it is excluded. simons 8016d 07h /
988 ORP architecture supported. simons 8016d 22h /
987 ORP architecture supported. simons 8017d 06h /
986 outputs out of function are not registered anymore markom 8017d 06h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8017d 18h /
984 Disable SB until it is tested lampret 8017d 18h /
983 First checkin lampret 8017d 20h /
982 Moved to sim/bin lampret 8017d 20h /
981 First checkin. lampret 8017d 20h /
980 Removed sim.tcl that shouldn't be here. lampret 8017d 20h /
979 Removed old test case binaries. lampret 8017d 20h /
978 Added variable delay for SRAM. lampret 8017d 20h /
977 Added store buffer. lampret 8017d 20h /
976 Added store buffer lampret 8017d 20h /
975 First checkin lampret 8017d 20h /
974 Enabled what works on or1ksim and disabled other tests. lampret 8017d 22h /

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