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Rev Log message Author Age Path
986 outputs out of function are not registered anymore markom 8002d 01h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8002d 13h /
984 Disable SB until it is tested lampret 8002d 13h /
983 First checkin lampret 8002d 15h /
982 Moved to sim/bin lampret 8002d 15h /
981 First checkin. lampret 8002d 15h /
980 Removed sim.tcl that shouldn't be here. lampret 8002d 15h /
979 Removed old test case binaries. lampret 8002d 15h /
978 Added variable delay for SRAM. lampret 8002d 15h /
977 Added store buffer. lampret 8002d 15h /
976 Added store buffer lampret 8002d 15h /
975 First checkin lampret 8002d 15h /
974 Enabled what works on or1ksim and disabled other tests. lampret 8002d 17h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8004d 21h /
972 Interrupt suorces fixed. simons 8004d 22h /
971 Now even keyboard test passes. simons 8005d 00h /
970 Testbench is now running on ORP architecture platform. simons 8005d 13h /
969 Checking in except directory. lampret 8006d 05h /
968 Checking in utils directory. lampret 8006d 05h /
967 Checking in mul directory. lampret 8006d 05h /
966 Checking in cbasic directory. lampret 8006d 05h /
965 Checking in basic directory. lampret 8006d 05h /
964 Checking in support directory. lampret 8006d 05h /
963 This commit was manufactured by cvs2svn to create tag 'rel_2'. 8006d 05h /
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8006d 05h /
961 uart16550 RTL files renamed/added/removed. lampret 8006d 05h /
960 Directory cleanup. lampret 8006d 05h /
959 Fixed size of generic flash/sram to exactly 2MB lampret 8007d 05h /
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8007d 05h /
957 Flash at 0x04000000 RAM at 0x00000000. Only MMU test works. simons 8007d 15h /

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