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Rev Log message Author Age Path
30 LGPL header homer.xing 4518d 15h /
29 default net type is wire homer.xing 4525d 12h /
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 4525d 15h /
27 definition for undefined wire homer.xing 4525d 15h /
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 4531d 11h /
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 4531d 12h /
24 LGPL claim in each source hdl file homer.xing 4539d 12h /
23 LGPL license text homer.xing 4539d 12h /
22 Change TAB to space homer.xing 4539d 13h /
21 Add detailed input data capture condition in the document homer.xing 4539d 14h /
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 4540d 16h /
19 Update synthesis result homer.xing 4541d 09h /
18 add synthesis result homer.xing 4541d 09h /
17 use logic for $f3m_mux6$ homer.xing 4541d 11h /
16 Add synthesis configuration files homer.xing 4541d 14h /
15 add document. ha ha ha homer.xing 4541d 15h /
14 Move constraint file homer.xing 4541d 16h /
13 Add document and synthesis directories homer.xing 4541d 16h /
12 Simplify the interface of the core. homer.xing 4541d 16h /
11 Cheers! as fast as a rocket homer.xing 4542d 12h /
10 Ho ho, better circuit homer.xing 4543d 06h /
9 Add constrains file for ISE homer.xing 4544d 10h /
8 Finished Tate Pairing. Ha ha ha homer.xing 4544d 11h /
7 Finish inversion @ f33m homer.xing 4552d 16h /
6 add testbench for $f33m$. homer.xing 4553d 15h /
5 rename director : verilog/ -> rtl/ homer.xing 4553d 15h /
4 add testbench homer.xing 4554d 13h /
3 finish Duursma Lee algorithm. doing f33m module homer.xing 4554d 13h /
2 upload code for Duursma-Lee algorithm. I am still developing them. homer.xing 4555d 13h /
1 The project and the structure was created root 4555d 13h /

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