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Rev Log message Author Age Path
93 Added a test application! mihad 7698d 08h /
92 Update! mihad 7698d 08h /
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7733d 22h /
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7733d 22h /
89 Burst 2 error fixed. mihad 7769d 23h /
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7775d 22h /
87 Updated acording to RTL changes. mihad 7787d 19h /
86 Entered the option to disable no response counter in wb master. mihad 7787d 19h /
85 Changed Vendor ID defines. mihad 7788d 00h /
84 Changed vendor ID. mihad 7791d 18h /
83 Cleaned up the code. No functional changes. mihad 7816d 17h /
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7830d 13h /
81 Updated synchronization in top level fifo modules. mihad 7830d 13h /
80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7833d 18h /
79 Updated. mihad 7833d 18h /
78 Old files with wrong names removed. mihad 7833d 18h /
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7833d 18h /
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7836d 18h /
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7839d 19h /
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7839d 19h /
73 Bug fixes, testcases added. mihad 7839d 19h /
72 *** empty log message *** mihad 7886d 23h /
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7894d 14h /
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7931d 22h /
69 Changed BIST signal names etc.. mihad 7931d 22h /
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7935d 07h /
67 Changed BIST signals for RAMs. tadejm 7935d 12h /
66 Changed empty status generation in pciw_fifo_control.v mihad 7938d 23h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7941d 21h /
64 The testcase I just added in previous revision repaired mihad 7941d 23h /

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