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Rev Log message Author Age Path
121 Added address constants for uart access (memory mapped I/O) trinklhar 6402d 13h /
120 Added UART module to memory entity trinklhar 6402d 13h /
119 Uart wieder ausgebaut trinklhar 6403d 08h /
118 insert Uart address constant trinklhar 6403d 08h /
117 Uart im mem_stage trinklhar 6403d 08h /
116 writes to uart when write to reg 0 trinklhar 6404d 14h /
115 *** empty log message *** trinklhar 6405d 04h /
114 Uart 0.3 trinklhar 6406d 08h /
113 Uart reset funkt trinklhar 6406d 09h /
112 Uart drin aber signale nicht eingebunden trinklhar 6406d 11h /
111 - Fixed bug where certain opcodes did not check for availability of
registers.		 cwalter 6409d 03h /
110 - Added missing file to CVS. cwalter 6409d 10h /
109 - Assembler code for ST produced wrong instruction format. cwalter 6410d 01h /
108 no message cwalter 6410d 01h /
107 - Added new example for memory testing. cwalter 6410d 01h /
106 - ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT. cwalter 6410d 01h /
105 - OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT. cwalter 6410d 01h /
104 - Added missing signal dmem_data_in. cwalter 6410d 02h /
103 - Added simulation for memory to behavioral.
- Added empty mif file for memory.		 cwalter 6410d 02h /
102 changed data pitch ustadler 6412d 07h /
101 - Signals for memory block where not always set. This resulted in a latch. cwalter 6412d 07h /
100 - Signal clear_in was missing in sensitivity list. cwalter 6412d 08h /
99 - Fixed problem with barrel shifter input signals where a latch has been
synthesized.		 cwalter 6412d 08h /
98 - Applied indenting tool. cwalter 6412d 08h /
97 Fixed bug: only set branch and clear signals if branch is actually executed. jlechner 6412d 09h /
96 - SR register is now computed in ALU stage. cwalter 6412d 09h /
95 - Write back now only updates SR in case of a LOAD. cwalter 6412d 09h /
94 Added signal from ex stage to register lock unit for clearing all register locks
when a branch is executed.		 jlechner 6412d 09h /
93 Changed behavior on branch. Current PC is immeadiately taken from ex stage alu result. jlechner 6412d 09h /
92 Added logic for inserting a nop instruction when the pipeline is cleared. jlechner 6412d 09h /

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