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Rev Log message Author Age Path
38 Port Name clean up dinesha 4523d 20h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4523d 21h /
36 Clean up dinesha 4524d 12h /
35 Updated the New Documents - ver 0.1 dinesha 4524d 14h /
34 Removed the older version dinesha 4524d 14h /
33 clean up dinesha 4524d 14h /
32 Debug is enable through +define dinesha 4526d 13h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4526d 13h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4526d 13h /
29 SDRAM top and core related run file list are added into svn dinesha 4526d 13h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4526d 14h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4527d 12h /
26 invalid log files are removed dinesha 4527d 12h /
25 tb.sv is renamed as tb_top dinesha 4527d 12h /
24 Clean Up dinesha 4527d 12h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4528d 17h /
22 Pad sdram clock added dinesha 4528d 17h /
21 Clean up dinesha 4528d 17h /
20 8 Bit SDARM support is added dinesha 4530d 12h /
19 8 Bit SDRAM Support added dinesha 4530d 12h /
18 8 Bit SDRAM Support is added dinesha 4530d 12h /
17 micron 8 bit memory models are added into svn dinesha 4530d 12h /
16 8 Bit SDRAM Support is added dinesha 4530d 12h /
15 Port cleanup dinesha 4533d 13h /
14 Unnecessary device config are removed dinesha 4533d 13h /
13 column bit are made progrmmable dinesha 4533d 13h /
12 Column Bits are made programmable dinesha 4533d 13h /
11 SDRAM Specification document added into SVN dinesha 4536d 14h /
10 Waveform files are added into SVN dinesha 4536d 14h /
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4537d 14h /

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