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Rev Log message Author Age Path
71 Warning cleanup dinesha 4068d 20h /
70 Warning Cleanup dinesha 4068d 20h /
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4068d 21h /
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4068d 21h /
67 time scale removed dinesha 4138d 19h /
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4386d 20h /
65 Updated Log file with CAS latency support 4,5 dinesha 4387d 04h /
64 CAS Latency support added for 4,5 dinesha 4387d 04h /
63 FPGA Bench mark results are added dinesha 4506d 03h /
62 Synthesis constraint for simplify dinesha 4506d 03h /
61 RTL file list are added into SVN dinesha 4506d 04h /
60 warning cleanup dinesha 4506d 04h /
59 Control path request and data are register now for better FPGA timing dinesha 4506d 04h /
58 Read Data is register on RD_FAST=0 case dinesha 4506d 04h /
57 Synthesis constraints are added dinesha 4506d 19h /
56 FPGA Synth optimisation dinesha 4506d 20h /
55 FPGA Synthesis timing optimisation dinesha 4506d 20h /
54 FPGA Timing Optimisation dinesha 4509d 18h /
53 Test bench upgradation dinesha 4510d 18h /
52 Documentation update for request control and transfer control block dinesha 4510d 18h /
51 FPGA relating timing optimisation done dinesha 4510d 18h /
50 Bug fix the request length is fixe dinesha 4512d 22h /
49 clean up dinesha 4513d 21h /
48 top-level cleanup dinesha 4513d 21h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4513d 21h /
46 test bench upgrade + rtl cleanup dinesha 4515d 22h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4516d 02h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4518d 00h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4518d 02h /
42 Bug fix in read access is fixed dinesha 4518d 02h /

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