URL https://opencores.org/ocsvn/simple_fm_receiver/simple_fm_receiver/trunk

Subversion Repositories simple_fm_receiver

[/] - Rev 23

Rev	Log message	Author	Age	Path
23	Disable clear signal.	arif_endro	5855d 00h	/
22	Update last bit output assignment method.	arif_endro	5855d 00h	/
21	This commit was manufactured by cvs2svn to create tag 'version_1_1'.		7040d 01h	/
20	New Version	arif_endro	7040d 01h	/
19	Screen shot from chipscope analyzer view, this is how this design work.	arif_endro	7046d 00h	/
18	This bit files generates better wave than previous (i.e. more smooth)	arif_endro	7046d 02h	/
17	Initial Checkin	arif_endro	7053d 23h	/
16	Changes constan and minor fix	arif_endro	7057d 02h	/
15	Xilinx FPGA XC2V2000 bit files the first version.	arif_endro	7060d 00h	/
14	* empty log message *	arif_endro	7064d 22h	/
13	Update License	arif_endro	7075d 23h	/
12	Update License Change reset signal handle	arif_endro	7075d 23h	/
11	Update License Change reset signal handle	arif_endro	7076d 00h	/
10	Added script for generating cos ROM.	arif_endro	7086d 02h	/
9	Added documentation	arif_endro	7103d 01h	/
8	This commit was manufactured by cvs2svn to create tag 'okinawa_1'.		7117d 02h	/
7	To view chipscope exported output using ModelSim waveform window	arif_endro	7117d 02h	/
6	Added Xilinx FPGA implementation (e.g. connector to ILA, ICON, and VIO)	arif_endro	7118d 03h	/
5	Added interface in/out and testing paralelly (e.g. square and triangular)	arif_endro	7118d 04h	/
4	Fix elsif and if statement	arif_endro	7120d 21h	/
3	This commit was manufactured by cvs2svn to create tag 'VSFR_1'.		7124d 04h	/
2	Initial releases	arif_endro	7124d 04h	/
1	Standard project directories initialized by cvs2svn.		7124d 04h	/