URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] - Rev 35

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Rev	Log message	Author	Age	Path
35	Top level test bench for receiver. NB! Not complete.	gedra	7326d 19h	/
34	Converter to numeric_std and added hex functions	gedra	7326d 19h	/
33	Minor update.	gedra	7326d 19h	/
32	Wishbone bus utilities.	gedra	7328d 13h	/
31	Added data output.	gedra	7328d 13h	/
30	Added Wishbone bus cycle decoder.	gedra	7329d 15h	/
29	Wishbone bus cycle decoder.	gedra	7329d 15h	/
28	Delint'ed and changed name of architecture.	gedra	7333d 23h	/
27	Alternate dual port memory implementation for Altera FPGA's.	gedra	7334d 14h	/
26	Fixed a few bugs.	gedra	7336d 14h	/
25	Changed status reg. declaration	gedra	7336d 14h	/
24	Added channel status decoding.	gedra	7336d 14h	/
23	Added frame decoder	gedra	7336d 14h	/
22	Renamed generic	gedra	7339d 15h	/
21	Renamed generic's and modified recevier configuration register	gedra	7339d 15h	/
20	Renamed generic and cleaned some lint's	gedra	7339d 15h	/
19	Added frame decoder and sample extractor	gedra	7339d 15h	/
18	Frame decoder and sample extractor	gedra	7339d 15h	/
17	Cleaned up lint warnings.	gedra	7342d 14h	/
16	Added dual port ram.	gedra	7343d 13h	/
15	Generic dual port ram model.	gedra	7343d 13h	/
14	Receiver component declarations.	gedra	7345d 15h	/
13	Cleaned up lint warnings.	gedra	7346d 17h	/
12	Simple test bench for rx_phase_det.vhd.	gedra	7346d 17h	/
11	Early version of the bi-phase mark decoder.	gedra	7346d 17h	/
10	Recevier status register	gedra	7347d 15h	/
9	Channel status/user data capture register	gedra	7347d 15h	/
8	Cleaned up lint warnings.	gedra	7348d 17h	/
7	Receiver version register.	gedra	7349d 15h	/
6	Generic event register. Used in both receiver and transmitter.	gedra	7349d 15h	/

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[/] - Rev 35

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