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Rev Log message Author Age Path
28 - bugfix in pipeline re-sync of d/i-cache
- optimized bus unit
- minor edits... ^^
zero_gravity 4481d 22h /
27 updated "sim" folder
- error in testbench environment
-> old components
-> weren't compatible to new core version anymore
=> FIXED! ;)
- thanks to Pratip Mukherjee
zero_gravity 4485d 21h /
26 bug fixes:
- change in priority for cache miss/dirty/io_access
- memory based pc modifications
- removed internal timer
zero_gravity 4486d 22h /
25 bug-fix in cache component:
-> error in cache page-access history manager
zero_gravity 4495d 05h /
24 - changed back to original oc svn folder structure
- bug-fix in documentary
- WB_ERR_I signal added to terminate wishbone bus access
- bug-fix: system mode register set and privs
zero_gravity 4496d 04h /
23 zero_gravity 4496d 05h /
22 changed back to original svn folder structure zero_gravity 4496d 05h /
21 smaller, faster, better ;)
* bug-fix: load-multiple instructions
* new cache-control system
* direct-accessible IO area can be specified
* extended demo implementation
zero_gravity 4503d 00h /
20 - update of data sheet -> note for system memory map layout and d-cache configuration zero_gravity 4518d 18h /
19 - simulation test bench added
- example for compatible wishbone fabric/SoC added
- block transfers from user bank updated
zero_gravity 4518d 22h /
18 makefile update to ensure no thumb code is generated zero_gravity 4524d 03h /
17 small synthesis-friendly update of memory components zero_gravity 4526d 20h /
16 WB_TGC(5) signal fixed (indicating instruction/data fetch),
coprocessor read-access bug fixed
zero_gravity 4526d 22h /
15 new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;) zero_gravity 4527d 03h /
14 - corrected stupid error in access arbiter
- updated minor issues
zero_gravity 4664d 23h /
13 - corrected endianess converter for memory access
- corrected error in temporal dependence detector
zero_gravity 4665d 19h /
12 - corrected error in memory write back interface
- corrected immediate/register offset for byte/halfword memory access
zero_gravity 4666d 00h /
11 zero_gravity 4669d 04h /
10 New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface.
Ready to execute assembled ARM ASM code, arm-elf-assembler included.
zero_gravity 4669d 05h /
9 documentation updated zero_gravity 4759d 02h /
8 documentation uploaded ;) zero_gravity 4760d 21h /
7 - new register file architecture
- fixed multi-cycle op bug
- architecture update
zero_gravity 4764d 19h /
6 new core version - now with arm compatible memory interface zero_gravity 4770d 19h /
5 memory interface updated zero_gravity 4821d 18h /
4 new instruction cycle controller - interrupt call bug seems to be fixed zero_gravity 4823d 20h /
3 zero_gravity 4825d 03h /
2 zero_gravity 4837d 04h /
1 The project and the structure was created root 4840d 11h /

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