| Rev |
Log message |
Author |
Age |
Path |
| 34 |
- bug fixed in carry-flag generation logic (not-carry = borrow flag)
- missing signal in STORM_TOP.vhd added |
zero_gravity |
4443d 03h |
/ |
| 33 |
- branch-and-exchange instruction (BX) support added
=> for BX Rn, where Rn(0) = '0', behavior like branch to address = Rn
=> for BX Rn, where Rn(0) = '1', triggering undefined instruction trap |
zero_gravity |
4449d 12h |
/ |
| 32 |
- bug-fix of block transfer operations
=> now fully ARM-compatible |
zero_gravity |
4451d 00h |
/ |
| 31 |
- small documentary edits
- CACHE.vhd modified for better synthesis results
- BUS_UNIT.vhd update to fulfill WB specs |
zero_gravity |
4453d 10h |
/ |
| 30 |
- minor edits in doc |
zero_gravity |
4458d 11h |
/ |
| 29 |
- specific IO area is now auto protected
- Wishbone compatibility extended
- cache flush optimized
- accelerated bus cycles due to less overhead |
zero_gravity |
4459d 11h |
/ |
| 28 |
- bugfix in pipeline re-sync of d/i-cache
- optimized bus unit
- minor edits... ^^ |
zero_gravity |
4470d 14h |
/ |
| 27 |
updated "sim" folder
- error in testbench environment
-> old components
-> weren't compatible to new core version anymore
=> FIXED! ;)
- thanks to Pratip Mukherjee |
zero_gravity |
4474d 13h |
/ |
| 26 |
bug fixes:
- change in priority for cache miss/dirty/io_access
- memory based pc modifications
- removed internal timer |
zero_gravity |
4475d 13h |
/ |
| 25 |
bug-fix in cache component:
-> error in cache page-access history manager |
zero_gravity |
4483d 21h |
/ |
| 24 |
- changed back to original oc svn folder structure
- bug-fix in documentary
- WB_ERR_I signal added to terminate wishbone bus access
- bug-fix: system mode register set and privs |
zero_gravity |
4484d 20h |
/ |
| 23 |
|
zero_gravity |
4484d 20h |
/ |
| 22 |
changed back to original svn folder structure |
zero_gravity |
4484d 20h |
/ |
| 21 |
smaller, faster, better ;)
* bug-fix: load-multiple instructions
* new cache-control system
* direct-accessible IO area can be specified
* extended demo implementation |
zero_gravity |
4491d 15h |
/ |
| 20 |
- update of data sheet -> note for system memory map layout and d-cache configuration |
zero_gravity |
4507d 10h |
/ |
| 19 |
- simulation test bench added
- example for compatible wishbone fabric/SoC added
- block transfers from user bank updated |
zero_gravity |
4507d 14h |
/ |
| 18 |
makefile update to ensure no thumb code is generated |
zero_gravity |
4512d 18h |
/ |
| 17 |
small synthesis-friendly update of memory components |
zero_gravity |
4515d 12h |
/ |
| 16 |
WB_TGC(5) signal fixed (indicating instruction/data fetch),
coprocessor read-access bug fixed |
zero_gravity |
4515d 14h |
/ |
| 15 |
new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;) |
zero_gravity |
4515d 18h |
/ |
| 14 |
- corrected stupid error in access arbiter
- updated minor issues |
zero_gravity |
4653d 15h |
/ |
| 13 |
- corrected endianess converter for memory access
- corrected error in temporal dependence detector |
zero_gravity |
4654d 10h |
/ |
| 12 |
- corrected error in memory write back interface
- corrected immediate/register offset for byte/halfword memory access |
zero_gravity |
4654d 16h |
/ |
| 11 |
|
zero_gravity |
4657d 20h |
/ |
| 10 |
New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface.
Ready to execute assembled ARM ASM code, arm-elf-assembler included. |
zero_gravity |
4657d 20h |
/ |
| 9 |
documentation updated |
zero_gravity |
4747d 18h |
/ |
| 8 |
documentation uploaded ;) |
zero_gravity |
4749d 12h |
/ |
| 7 |
- new register file architecture
- fixed multi-cycle op bug
- architecture update |
zero_gravity |
4753d 10h |
/ |
| 6 |
new core version - now with arm compatible memory interface |
zero_gravity |
4759d 11h |
/ |
| 5 |
memory interface updated |
zero_gravity |
4810d 10h |
/ |
