OpenCores
URL https://opencores.org/ocsvn/t51/t51/trunk

Subversion Repositories t51

[/] - Rev 51

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
51 New directory structure. root 5638d 09h /
50 initial version andreas 6337d 22h /
49 some improvements andreas 6501d 08h /
48 *** empty log message *** andreas 6669d 21h /
47 updated t8052 core andreas 6670d 04h /
46 some updates andreas 6670d 04h /
45 *** empty log message *** andreas 6670d 04h /
44 some updates and bugfixes andreas 6670d 04h /
43 bugfix for interrupts at stalled instructions andreas 6752d 22h /
42 *** empty log message *** andreas 6771d 20h /
41 some updates andreas 6771d 20h /
40 *** empty log message *** andreas 6771d 21h /
39 some updates for T8032 andreas 6771d 21h /
38 some updates andreas 6781d 04h /
37 some updates andreas 6781d 04h /
36 some updates andreas 6781d 07h /
35 some updates andreas 6781d 08h /
34 bugfix for mode 0 andreas 6790d 00h /
33 bugfix for JBC instruction andreas 6802d 05h /
32 bugfix for two subsequent movx instructions andreas 6839d 00h /
31 update andreas 6924d 23h /
30 Made some bugfixes andreas 6926d 02h /
29 Removed UNISIM library jesus 7936d 06h /
28 Added -n option and component declaration jesus 7964d 03h /
27 Added Leonardo .ucf generation jesus 7964d 03h /
26 Updated for ISE 5.1 jesus 7970d 23h /
25 Fixed typo jesus 7980d 15h /
24 Fixed for ISE 5.1 jesus 7980d 15h /
23 Xilinx SSRAM, initial release jesus 7990d 17h /
22 Removed write through jesus 8018d 14h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.