| Rev |
Log message |
Author |
Age |
Path |
| 35 |
Added a little assembler ruby script. Basically, I plan on levaraging the power of Ruby as a DSL to very easily create an assembler, rather than having to parse everything myself. |
earlz |
4486d 16h |
/ |
| 34 |
Implemented load and store instructions (`mov reg, [reg]` and `mov [reg], reg` respectively) |
earlz |
4487d 07h |
/ |
| 33 |
Added more test cases for push/pop. More are still needed though
Fixed SP increment/decrementing
Added new opcode `mov reg,reg` so debugging isn't such a pain |
earlz |
4487d 10h |
/ |
| 32 |
Finished up changes needed to make memory reading actually work.
Push and Pop now work |
earlz |
4487d 11h |
/ |
| 31 |
Removed the infamous TRData latch from ALU. Now synthesizes (sorta) warning free. No latches are used. |
earlz |
4488d 07h |
/ |
| 30 |
After a long weekend of thinking how to do this.. I've decided instead to not strive for a single-cycle computer.
Now, instead, ALU operations will be 2 cycle along with memory operations, and data movement operations are still 1 cycle |
earlz |
4488d 07h |
/ |
| 29 |
Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad. |
earlz |
4491d 14h |
/ |
| 28 |
Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers |
earlz |
4492d 09h |
/ |
| 27 |
Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later |
earlz |
4492d 15h |
/ |
| 26 |
Added extra check to make sure fetcher works properly after memory write |
earlz |
4492d 16h |
/ |
| 25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4492d 20h |
/ |
| 24 |
Good news, mov to IP actually works as expected! |
earlz |
4493d 13h |
/ |
| 23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4493d 14h |
/ |
| 22 |
Added to process sensitivity list to avoid warning and added ELSE for IR so it doesn't generate a latch |
earlz |
4494d 05h |
/ |
| 21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4494d 06h |
/ |
| 20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4495d 05h |
/ |
| 19 |
Got beginning of core/decoder for the CPU |
earlz |
4495d 07h |
/ |
| 18 |
Finished memory controller |
earlz |
4498d 17h |
/ |
| 17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4499d 06h |
/ |
| 16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4502d 09h |
/ |
| 15 |
Added README, LICENSE, and the (so far not created) incdec component |
earlz |
4504d 06h |
/ |
| 14 |
Added ALU with all the operations we'll need. Synthesizes as well trivially |
earlz |
4504d 14h |
/ |
| 13 |
Forgot about the new library I added |
earlz |
4504d 17h |
/ |
| 12 |
registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD |
earlz |
4504d 18h |
/ |
| 11 |
Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge |
earlz |
4508d 07h |
/ |
| 10 |
Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs |
earlz |
4508d 07h |
/ |
| 9 |
Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench |
earlz |
4508d 15h |
/ |
| 8 |
Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing |
earlz |
4509d 14h |
/ |
| 7 |
Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000) |
earlz |
4509d 16h |
/ |
| 6 |
Reworked memory code to hopefully synthesize better |
earlz |
4509d 20h |
/ |
