URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] - Rev 108

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
108	Added old uploaded documents to new repository.	root	5607d 03h	/
107	Added old uploaded documents to new repository.	root	5607d 09h	/
106	New directory structure.	root	5607d 09h	/
105	Timeout interrupt should be generated only when there is at least ony character in the fifo.	igorm	7176d 10h	/
104	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7333d 05h	/
103	Brandl Tobias repaired a bug regarding frame error in receiver when brake is received.	tadejm	7333d 05h	/
102	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7361d 07h	/
101	Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode.	tadejm	7361d 07h	/
100	Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs.	tadejm	7361d 08h	/
99	Added synchronizer flops for RX input.	tadejm	7361d 08h	/
98	Added to synchronize RX input to Wishbone clock.	tadejm	7361d 08h	/
97	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7416d 15h	/
96	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish.	tadejm	7416d 15h	/
95	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish.	tadejm	7416d 15h	/
94	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7416d 15h	/
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7416d 15h	/
92	This is revision 1.4, revision 1.5 was put there by mistake.	simons	7530d 08h	/
91	Removed files due to new complete testbench.	tadejm	7530d 23h	/
90	Add Flextronics header	avisha	7533d 06h	/
89	adjusted comment + define	dries	7613d 12h	/
88	added clearing the receiver fifo statuses on resets	gorban	7676d 01h	/
87	This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.	gorban	7706d 03h	/
86	restored include for uart_defines.v in uart_test.v	gorban	7976d 07h	/
85	Updated documentation to include latest changes.	gorban	8009d 23h	/
84	The uart_defines.v file is included again in sources.	gorban	8022d 22h	/
83	Reverted to include uart_defines.v file in other files again.	gorban	8022d 22h	/
82	Updated to work with latest core.	gorban	8029d 20h	/
81	Added lastest additions.	gorban	8029d 20h	/
80	Remove uart_fifo.v because it is replaced by other 2 files.	gorban	8029d 20h	/
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	8029d 20h	/

Browse

Tools

Subversion Repositories uart16550

[/] - Rev 108

Filtering Options