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Rev Log message Author Age Path
64 Warnings cleared. mohor 8245d 11h /
63 Synplicity was having troubles with the comment. mohor 8245d 11h /
62 Bug that was entered in the last update fixed (rx state machine). mohor 8246d 10h /
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8247d 04h /
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8247d 09h /
59 MSR register fixed. mohor 8250d 06h /
58 After reset modem status register MSR should be reset. mohor 8250d 09h /
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8251d 08h /
56 thre irq should be cleared only when being source of interrupt. mohor 8251d 09h /
55 some synthesis bugs fixed gorban 8251d 21h /
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8252d 10h /
53 Scratch register define added. mohor 8253d 10h /
52 Scratch register added gorban 8253d 23h /
51 Igor fixed break condition bugs gorban 8253d 23h /
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8258d 04h /
49 committed the debug interface file gorban 8259d 22h /
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8260d 21h /
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8265d 23h /
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8266d 21h /
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8267d 21h /
44 fixed more typo bugs gorban 8281d 21h /
43 lsr1r error fixed. mohor 8282d 04h /
42 ti_int_pnd error fixed. mohor 8282d 04h /
41 ti_int_d error fixed. mohor 8282d 04h /
40 Synthesis bugs fixed. Some other minor changes gorban 8284d 06h /
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8286d 04h /
38 small update to test interrupts gorban 8287d 01h /
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8287d 01h /
36 no message mohor 8292d 09h /
35 Fixes to break and timeout conditions gorban 8294d 04h /

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