URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] - Rev 116

Rev	Log message	Author	Age	Path
116	fix path of the axi rom module	ultro	2922d 19h	/
115	update for synth slack	ultro	2923d 13h	/
114	update cosmetic	ultro	2923d 14h	/
113	updates to take acu appart	ultro	2923d 14h	/
112	Added the prj missing files	ultro	2927d 03h	/
111	added comment	ultro	2943d 13h	/
110	updated MCS files to be downloaded to nexys4 DDR	ultro	2943d 13h	/
109	update for nexys 4 ddr	ultro	2943d 13h	/
108	update xdc for nexys 4 ddr	ultro	2943d 13h	/
107	crossbar update	ultro	2943d 13h	/
106	update core netlist	ultro	2943d 13h	/
105	migration nexys ddr	ultro	2943d 15h	/
104	iadd rstgen and clk wiard for ddr nexys4 TOP	ultro	2950d 15h	/
103	commit top for 128mbyte nexys4 ddr version	ultro	2960d 04h	/
102	committed 128mbytes boot code for nexys4 ddr	ultro	2960d 04h	/
101	add ddr interface mig7 xilinx xci ip	ultro	2960d 18h	/
100	add crossbar for nexys4 ddr with 128megabyte ram window	ultro	2960d 18h	/
99	remove phy_intn from xdc constraints as it is not used inside design wi th etherlite.	ultro	3002d 03h	/
98	update tbench and add mii to rmii converter ip from xilinx	ultro	3002d 12h	/
97	update periph and TOP	ultro	3002d 12h	/
96	update periph , uart is not inside	ultro	3002d 13h	/
95	update boot.mem accordingly to test.s cleanup	ultro	3004d 16h	/
94	clean up test.s	ultro	3004d 16h	/
93	added stub for keyboard	ultro	3005d 05h	/
92	added doc	ultro	3005d 06h	/
91	update netlists cosmetics	ultro	3005d 18h	/
90	updated cosmetic periph.v	ultro	3005d 19h	/
89	add 3x rtl files	ultro	3005d 20h	/
88	remove axi ip standalone	ultro	3005d 21h	/
87	update rtl for boot.mem	ultro	3005d 21h	/