URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] - Rev 119

Rev	Log message	Author	Age	Path
119	cleanup	ultro	2856d 11h	/
118	cleanup	ultro	2856d 11h	/
117	reset polarity in mig_b.prj for ddr2 was wrong , should be high	ultro	2903d 15h	/
116	fix path of the axi rom module	ultro	2917d 10h	/
115	update for synth slack	ultro	2918d 04h	/
114	update cosmetic	ultro	2918d 05h	/
113	updates to take acu appart	ultro	2918d 06h	/
112	Added the prj missing files	ultro	2921d 18h	/
111	added comment	ultro	2938d 04h	/
110	updated MCS files to be downloaded to nexys4 DDR	ultro	2938d 04h	/
109	update for nexys 4 ddr	ultro	2938d 05h	/
108	update xdc for nexys 4 ddr	ultro	2938d 05h	/
107	crossbar update	ultro	2938d 05h	/
106	update core netlist	ultro	2938d 05h	/
105	migration nexys ddr	ultro	2938d 06h	/
104	iadd rstgen and clk wiard for ddr nexys4 TOP	ultro	2945d 06h	/
103	commit top for 128mbyte nexys4 ddr version	ultro	2954d 20h	/
102	committed 128mbytes boot code for nexys4 ddr	ultro	2954d 20h	/
101	add ddr interface mig7 xilinx xci ip	ultro	2955d 09h	/
100	add crossbar for nexys4 ddr with 128megabyte ram window	ultro	2955d 09h	/
99	remove phy_intn from xdc constraints as it is not used inside design wi th etherlite.	ultro	2996d 18h	/
98	update tbench and add mii to rmii converter ip from xilinx	ultro	2997d 04h	/
97	update periph and TOP	ultro	2997d 04h	/
96	update periph , uart is not inside	ultro	2997d 04h	/
95	update boot.mem accordingly to test.s cleanup	ultro	2999d 07h	/
94	clean up test.s	ultro	2999d 07h	/
93	added stub for keyboard	ultro	2999d 20h	/
92	added doc	ultro	2999d 21h	/
91	update netlists cosmetics	ultro	3000d 09h	/
90	updated cosmetic periph.v	ultro	3000d 10h	/