URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] - Rev 123

Rev	Log message	Author	Age	Path
123	update core netlist	ultro	2828d 01h	/
122	update netlist cpu	ultro	2828d 05h	/
121	major update to support several board	ultro	2828d 07h	/
120	cleanup	ultro	2828d 08h	/
119	cleanup	ultro	2828d 08h	/
118	cleanup	ultro	2828d 08h	/
117	reset polarity in mig_b.prj for ddr2 was wrong , should be high	ultro	2875d 12h	/
116	fix path of the axi rom module	ultro	2889d 07h	/
115	update for synth slack	ultro	2890d 01h	/
114	update cosmetic	ultro	2890d 02h	/
113	updates to take acu appart	ultro	2890d 02h	/
112	Added the prj missing files	ultro	2893d 15h	/
111	added comment	ultro	2910d 01h	/
110	updated MCS files to be downloaded to nexys4 DDR	ultro	2910d 01h	/
109	update for nexys 4 ddr	ultro	2910d 01h	/
108	update xdc for nexys 4 ddr	ultro	2910d 01h	/
107	crossbar update	ultro	2910d 01h	/
106	update core netlist	ultro	2910d 01h	/
105	migration nexys ddr	ultro	2910d 03h	/
104	iadd rstgen and clk wiard for ddr nexys4 TOP	ultro	2917d 03h	/
103	commit top for 128mbyte nexys4 ddr version	ultro	2926d 16h	/
102	committed 128mbytes boot code for nexys4 ddr	ultro	2926d 16h	/
101	add ddr interface mig7 xilinx xci ip	ultro	2927d 06h	/
100	add crossbar for nexys4 ddr with 128megabyte ram window	ultro	2927d 06h	/
99	remove phy_intn from xdc constraints as it is not used inside design wi th etherlite.	ultro	2968d 15h	/
98	update tbench and add mii to rmii converter ip from xilinx	ultro	2969d 00h	/
97	update periph and TOP	ultro	2969d 00h	/
96	update periph , uart is not inside	ultro	2969d 01h	/
95	update boot.mem accordingly to test.s cleanup	ultro	2971d 04h	/
94	clean up test.s	ultro	2971d 04h	/