URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] - Rev 27

Rev	Log message	Author	Age	Path
27	initial commit, dual way simplex FIFO	unneback	5084d 15h	/
26	added ACTEL synthesis directive as define, +ACTEL	unneback	5084d 15h	/
25	DFF SR as separate logic	unneback	5224d 11h	/
24	updated fifo interfaces with re/rd and we/wr	unneback	5225d 02h	/
23		unneback	5227d 14h	/
22	async fifo with multiple queues	unneback	5227d 15h	/
21	added DFF SR	unneback	5241d 12h	/
20		unneback	5241d 19h	/
19	DFF with async clear and set for Altera cycloneIV	unneback	5243d 01h	/
18	ADDR and DATA width set to 8 resp 32	unneback	5243d 15h	/
17	based on updated versatile counter	unneback	5247d 14h	/
16	changed power of two style	unneback	5511d 00h	/
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5514d 17h	/
14	added PDF	unneback	5559d 00h	/
13	adr update	unneback	5560d 02h	/
12	no mux on dual port mem read	unneback	5572d 19h	/
11	name conflict wptr1 changed to wptr1_cnt etc	unneback	5572d 22h	/
10	rptr2	unneback	5572d 23h	/
9		unneback	5578d 19h	/
8		unneback	5578d 19h	/
7		unneback	5578d 19h	/
6		unneback	5578d 22h	/
5	async compare for fifo full and empty	unneback	5578d 22h	/
4		unneback	5579d 02h	/
3		unneback	5579d 02h	/
2		unneback	5579d 03h	/
1	The project was created and the structure was created	root	5580d 21h	/