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Rev Log message Author Age Path
32 fixed SYN directives marcus.erlandsson 4982d 16h /
31 port map unneback 5053d 08h /
30 port map unneback 5053d 09h /
29 ACTEL syn define unneback 5061d 06h /
28 ACTEL async dual way FIFO unneback 5068d 16h /
27 initial commit, dual way simplex FIFO unneback 5069d 07h /
26 added ACTEL synthesis directive as define, +ACTEL unneback 5069d 07h /
25 DFF SR as separate logic unneback 5209d 03h /
24 updated fifo interfaces with re/rd and we/wr unneback 5209d 18h /
23 unneback 5212d 06h /
22 async fifo with multiple queues unneback 5212d 07h /
21 added DFF SR unneback 5226d 04h /
20 unneback 5226d 11h /
19 DFF with async clear and set for Altera cycloneIV unneback 5227d 17h /
18 ADDR and DATA width set to 8 resp 32 unneback 5228d 07h /
17 based on updated versatile counter unneback 5232d 06h /
16 changed power of two style unneback 5495d 15h /
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5499d 09h /
14 added PDF unneback 5543d 16h /
13 adr update unneback 5544d 18h /
12 no mux on dual port mem read unneback 5557d 11h /
11 name conflict
wptr1 changed to wptr1_cnt etc
unneback 5557d 14h /
10 rptr2 unneback 5557d 15h /
9 unneback 5563d 10h /
8 unneback 5563d 10h /
7 unneback 5563d 10h /
6 unneback 5563d 14h /
5 async compare for fifo full and empty unneback 5563d 14h /
4 unneback 5563d 18h /
3 unneback 5563d 18h /

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