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Rev Log message Author Age Path
32 fixed SYN directives marcus.erlandsson 4973d 05h /
31 port map unneback 5043d 22h /
30 port map unneback 5043d 22h /
29 ACTEL syn define unneback 5051d 20h /
28 ACTEL async dual way FIFO unneback 5059d 05h /
27 initial commit, dual way simplex FIFO unneback 5059d 21h /
26 added ACTEL synthesis directive as define, +ACTEL unneback 5059d 21h /
25 DFF SR as separate logic unneback 5199d 16h /
24 updated fifo interfaces with re/rd and we/wr unneback 5200d 07h /
23 unneback 5202d 19h /
22 async fifo with multiple queues unneback 5202d 20h /
21 added DFF SR unneback 5216d 17h /
20 unneback 5217d 00h /
19 DFF with async clear and set for Altera cycloneIV unneback 5218d 06h /
18 ADDR and DATA width set to 8 resp 32 unneback 5218d 20h /
17 based on updated versatile counter unneback 5222d 19h /
16 changed power of two style unneback 5486d 05h /
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5489d 22h /
14 added PDF unneback 5534d 05h /
13 adr update unneback 5535d 07h /
12 no mux on dual port mem read unneback 5548d 00h /
11 name conflict
wptr1 changed to wptr1_cnt etc
unneback 5548d 03h /
10 rptr2 unneback 5548d 04h /
9 unneback 5554d 00h /
8 unneback 5554d 00h /
7 unneback 5554d 00h /
6 unneback 5554d 03h /
5 async compare for fifo full and empty unneback 5554d 03h /
4 unneback 5554d 07h /
3 unneback 5554d 07h /

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