URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] - Rev 33

Rev	Log message	Author	Age	Path
33	updated wb3wb3_bridge	unneback	4905d 19h	/
32	added vl_pll for ALTERA (cycloneIII)	unneback	4913d 04h	/
31	sync FIFO updated	unneback	4933d 00h	/
30	updated counter for level1 and level2 function	unneback	4933d 00h	/
29	updated counter for level1 and level2 function	unneback	4933d 00h	/
28	added sync simplex FIFO	unneback	4934d 02h	/
27	added sync simplex FIFO	unneback	4934d 02h	/
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4934d 03h	/
25	added sync FIFO	unneback	4934d 16h	/
24	added vl_dff_ce_set	unneback	4936d 00h	/
23	fixed port map error in async fifo 1r1w	unneback	4936d 15h	/
22	added binary counters	unneback	4936d 20h	/
21	reg -> wire in and or mux in logic	unneback	4937d 16h	/
20	naming convention vl_	unneback	4939d 03h	/
19	naming convention vl_	unneback	4939d 03h	/
18	naming convention vl_	unneback	4939d 03h	/
17		unneback	5002d 17h	/
16	converting utility for ROM	unneback	5003d 04h	/
15	added delay line	unneback	5009d 00h	/
14	reg -> wire for various signals	unneback	5009d 05h	/
13	cosmetic update	unneback	5009d 07h	/
12	added wishbone comliant modules	unneback	5010d 03h	/
11	async fifo simplex	unneback	5010d 18h	/
10	added dff_ce_clear	unneback	5012d 17h	/
9	added dff_ce_clear	unneback	5012d 17h	/
8	added dff_ce_clear	unneback	5012d 17h	/
7	mem update	unneback	5012d 18h	/
6	added library files	unneback	5025d 18h	/
5	memories added	unneback	5025d 19h	/
4	added counters	unneback	5029d 22h	/