URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] - Rev 38

Rev	Log message	Author	Age	Path
38	updated andor mux	unneback	4884d 02h	/
37	corrected polynom with length 20	unneback	4889d 22h	/
36	added generic andor_mux	unneback	4891d 07h	/
35	added vl_mux2_andor and vl_mux3_andor localparam	unneback	4891d 18h	/
34	added vl_mux2_andor and vl_mux3_andor	unneback	4891d 18h	/
33	updated wb3wb3_bridge	unneback	4904d 20h	/
32	added vl_pll for ALTERA (cycloneIII)	unneback	4912d 06h	/
31	sync FIFO updated	unneback	4932d 01h	/
30	updated counter for level1 and level2 function	unneback	4932d 02h	/
29	updated counter for level1 and level2 function	unneback	4932d 02h	/
28	added sync simplex FIFO	unneback	4933d 03h	/
27	added sync simplex FIFO	unneback	4933d 03h	/
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4933d 04h	/
25	added sync FIFO	unneback	4933d 18h	/
24	added vl_dff_ce_set	unneback	4935d 02h	/
23	fixed port map error in async fifo 1r1w	unneback	4935d 16h	/
22	added binary counters	unneback	4935d 22h	/
21	reg -> wire in and or mux in logic	unneback	4936d 18h	/
20	naming convention vl_	unneback	4938d 04h	/
19	naming convention vl_	unneback	4938d 04h	/
18	naming convention vl_	unneback	4938d 05h	/
17		unneback	5001d 18h	/
16	converting utility for ROM	unneback	5002d 05h	/
15	added delay line	unneback	5008d 02h	/
14	reg -> wire for various signals	unneback	5008d 07h	/
13	cosmetic update	unneback	5008d 09h	/
12	added wishbone comliant modules	unneback	5009d 05h	/
11	async fifo simplex	unneback	5009d 19h	/
10	added dff_ce_clear	unneback	5011d 18h	/
9	added dff_ce_clear	unneback	5011d 18h	/