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[/] - Rev 49

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Rev	Log message	Author	Age	Path
49	added WB_B4RAM with byte enable	unneback	4758d 03h	/
48	wb updated	unneback	4764d 21h	/
47	added help program for LFSR counters	unneback	4860d 00h	/
46	updated parity	unneback	4861d 02h	/
45	updated timing in io models	unneback	4862d 20h	/
44	added target independet IO functionns	unneback	4865d 20h	/
43	added logic for parity generation and check	unneback	4869d 23h	/
42	updated mux_andor	unneback	4873d 23h	/
41	typo in registers.v	unneback	4874d 00h	/
40	new build environment with custom.v added as a result file	unneback	4874d 01h	/
39	added simple port prio based wb arbiter	unneback	4874d 22h	/
38	updated andor mux	unneback	4874d 22h	/
37	corrected polynom with length 20	unneback	4880d 18h	/
36	added generic andor_mux	unneback	4882d 03h	/
35	added vl_mux2_andor and vl_mux3_andor localparam	unneback	4882d 14h	/
34	added vl_mux2_andor and vl_mux3_andor	unneback	4882d 14h	/
33	updated wb3wb3_bridge	unneback	4895d 16h	/
32	added vl_pll for ALTERA (cycloneIII)	unneback	4903d 02h	/
31	sync FIFO updated	unneback	4922d 21h	/
30	updated counter for level1 and level2 function	unneback	4922d 22h	/
29	updated counter for level1 and level2 function	unneback	4922d 22h	/
28	added sync simplex FIFO	unneback	4923d 23h	/
27	added sync simplex FIFO	unneback	4923d 23h	/
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4924d 00h	/
25	added sync FIFO	unneback	4924d 14h	/
24	added vl_dff_ce_set	unneback	4925d 21h	/
23	fixed port map error in async fifo 1r1w	unneback	4926d 12h	/
22	added binary counters	unneback	4926d 17h	/
21	reg -> wire in and or mux in logic	unneback	4927d 13h	/
20	naming convention vl_	unneback	4929d 00h	/

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[/] - Rev 49

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