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Rev Log message Author Age Path
50 added WB_B4RAM with byte enable unneback 4747d 12h /
49 added WB_B4RAM with byte enable unneback 4747d 12h /
48 wb updated unneback 4754d 06h /
47 added help program for LFSR counters unneback 4849d 09h /
46 updated parity unneback 4850d 11h /
45 updated timing in io models unneback 4852d 05h /
44 added target independet IO functionns unneback 4855d 05h /
43 added logic for parity generation and check unneback 4859d 08h /
42 updated mux_andor unneback 4863d 08h /
41 typo in registers.v unneback 4863d 09h /
40 new build environment with custom.v added as a result file unneback 4863d 09h /
39 added simple port prio based wb arbiter unneback 4864d 06h /
38 updated andor mux unneback 4864d 06h /
37 corrected polynom with length 20 unneback 4870d 03h /
36 added generic andor_mux unneback 4871d 11h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4871d 22h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4871d 23h /
33 updated wb3wb3_bridge unneback 4885d 01h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4892d 10h /
31 sync FIFO updated unneback 4912d 06h /
30 updated counter for level1 and level2 function unneback 4912d 06h /
29 updated counter for level1 and level2 function unneback 4912d 06h /
28 added sync simplex FIFO unneback 4913d 08h /
27 added sync simplex FIFO unneback 4913d 08h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4913d 09h /
25 added sync FIFO unneback 4913d 22h /
24 added vl_dff_ce_set unneback 4915d 06h /
23 fixed port map error in async fifo 1r1w unneback 4915d 21h /
22 added binary counters unneback 4916d 02h /
21 reg -> wire in and or mux in logic unneback 4916d 22h /

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