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Rev Log message Author Age Path
51 added WB_B4RAM with byte enable unneback 4751d 22h /
50 added WB_B4RAM with byte enable unneback 4751d 22h /
49 added WB_B4RAM with byte enable unneback 4751d 22h /
48 wb updated unneback 4758d 16h /
47 added help program for LFSR counters unneback 4853d 19h /
46 updated parity unneback 4854d 21h /
45 updated timing in io models unneback 4856d 15h /
44 added target independet IO functionns unneback 4859d 15h /
43 added logic for parity generation and check unneback 4863d 18h /
42 updated mux_andor unneback 4867d 18h /
41 typo in registers.v unneback 4867d 19h /
40 new build environment with custom.v added as a result file unneback 4867d 20h /
39 added simple port prio based wb arbiter unneback 4868d 17h /
38 updated andor mux unneback 4868d 17h /
37 corrected polynom with length 20 unneback 4874d 13h /
36 added generic andor_mux unneback 4875d 22h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4876d 09h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4876d 09h /
33 updated wb3wb3_bridge unneback 4889d 11h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4896d 21h /
31 sync FIFO updated unneback 4916d 16h /
30 updated counter for level1 and level2 function unneback 4916d 17h /
29 updated counter for level1 and level2 function unneback 4916d 17h /
28 added sync simplex FIFO unneback 4917d 18h /
27 added sync simplex FIFO unneback 4917d 18h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4917d 19h /
25 added sync FIFO unneback 4918d 09h /
24 added vl_dff_ce_set unneback 4919d 16h /
23 fixed port map error in async fifo 1r1w unneback 4920d 07h /
22 added binary counters unneback 4920d 12h /

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