URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 105

Rev	Log message	Author	Age	Path
105	versatile_mem modules naming	unneback	4934d 07h	/
104	versatile_mem modules naming	unneback	4934d 07h	/
103	added new block diagram pictures and texi source	unneback	4963d 01h	/
102	cleaning up	unneback	4965d 07h	/
101	cleaning up	unneback	4965d 07h	/
100		unneback	4965d 07h	/
99	updated stimuli with automatic check	unneback	4965d 07h	/
98	updates	unneback	5068d 12h	/
97	updated tb and sdram16	unneback	5069d 01h	/
96	doc update	unneback	5099d 13h	/
95	new files	unneback	5104d 02h	/
94	new TB	unneback	5112d 09h	/
93		unneback	5123d 07h	/
92		unneback	5123d 07h	/
91		unneback	5123d 07h	/
90		unneback	5123d 07h	/
89		unneback	5123d 07h	/
88		unneback	5123d 07h	/
87		unneback	5123d 07h	/
86		mikaeljf	5175d 14h	/
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5176d 14h	/
84		mikaeljf	5180d 13h	/
83		mikaeljf	5181d 08h	/
82		mikaeljf	5181d 13h	/
81		mikaeljf	5182d 09h	/
80		mikaeljf	5182d 10h	/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5220d 00h	/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5222d 07h	/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5230d 05h	/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5235d 06h	/