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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

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Rev Log message Author Age Path
91 unneback 5188d 07h /
90 unneback 5188d 07h /
89 unneback 5188d 07h /
88 unneback 5188d 07h /
87 unneback 5188d 08h /
86 mikaeljf 5240d 15h /
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5241d 15h /
84 mikaeljf 5245d 14h /
83 mikaeljf 5246d 09h /
82 mikaeljf 5246d 13h /
81 mikaeljf 5247d 10h /
80 mikaeljf 5247d 11h /
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5285d 01h /
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5287d 08h /
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5295d 06h /
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5300d 07h /
75 mikaeljf 5300d 08h /
74 Minor update of rtl Makefile. mikaeljf 5304d 07h /
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5304d 08h /
72 Restored lost revisions 69 and 70. mikaeljf 5304d 09h /
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5304d 10h /
70 mikaeljf 5307d 16h /
69 mikaeljf 5308d 12h /
68 cleaqnup unneback 5310d 01h /
67 added FSM for wb if unneback 5310d 01h /
66 unneback 5310d 04h /
65 added unneback 5310d 04h /
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5311d 03h /
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5311d 11h /
62 Added note to sdr_16_defines.v asking if it's still used julius 5311d 13h /

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