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Subversion Repositories vga_lcd

[/] - Rev 27

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Rev	Log message	Author	Age	Path
27	Added 32bpp Fixed some typos Added bandwidth section	rherveille	8203d 01h	/
26	Added 32bpp tests	rherveille	8203d 01h	/
25	C-include file. Initial release	rherveille	8269d 19h	/
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8276d 22h	/
23	Added Copyright/Licence header	rherveille	8277d 17h	/
22	VGA Core v2.0 Document revision 0.7	rherveille	8297d 14h	/
21	VGA Core v2.0 Document revision 0.7	rherveille	8297d 14h	/
20	Switched parameter order.	rherveille	8306d 18h	/
19	Major revisions throughout the core. Moved Color Lookup Table inside core. Changed control & status register contents. Changed port names to be conform to new naming convention. Fixed bug in CAB assertion. Changed video memory address generation. and many more ....	rherveille	8306d 20h	/
18	Removed files. They are not used anymore.	rherveille	8335d 17h	/
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8335d 17h	/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8362d 23h	/
15	Created directory structure (documentation, vhdl, verilog)	rherveille	8398d 13h	/
14	Added CLUT bank switching. Replaced multiplier with simple counters. Fixed timing bug.	rherveille	8399d 08h	/
13	Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore.	rherveille	8399d 20h	/
12	Added new top-level and sub-level (vga_and_clut.vhd & csm.vhd); adds color-lookup-table to the VGA core (i.e. on-chip CLUT). Ram generation has been tested with Altera and Xilinx parts.	rherveille	8409d 00h	/
11	Major bug fixes in Wishbone Master and ColorProcessor blocks. Core did not respond correctly to delayed ACK_I signals. Added built-in Color Lookup Tables.	rherveille	8409d 00h	/
10	Design now uses Xilinx-BlockRAMs instead of selectRAM	rherveille	8415d 16h	/
9	no message	rherveille	8416d 09h	/
8	Revised core. Removed unused signals	rherveille	8421d 17h	/
7	revised counter.vhd	rherveille	8425d 19h	/
6	no message	rherveille	8426d 19h	/
5	Fixed a bug in wishbone master. Updated simulation files also	rherveille	8430d 19h	/
4	changed wishbone address sections.	rherveille	8441d 19h	/
3	This commit was manufactured by cvs2svn to create tag 'beta'.		8454d 23h	/
2	initial release	rherveille	8454d 23h	/
1	Standard project directories initialized by cvs2svn.		8454d 23h	/

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[/] - Rev 27

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