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Rev Log message Author Age Path
52 Numerous updates and added checks rherveille 7739d 11h /
51 Forgot to change document revision number rherveille 7787d 06h /
50 Forgot to change document revision rherveille 7787d 06h /
49 Added WISHBONE revB.3 signals rherveille 7787d 07h /
48 WISHBONE revB.3 signals added rherveille 7787d 07h /
47 Added wb_b3_check
Removed ud_cnt, ro_cnt		 rherveille 7788d 04h /
46 Added WISHBONE revB.3 sanity checks rherveille 7788d 04h /
45 Changed timing generator; made it smaller and easier. rherveille 7788d 08h /
44 Changed timing section in VGA core, changed testbench accordingly.
Fixed bug in 'timing check' test.		 rherveille 7788d 09h /
43 Added WISHBONE revB.3 Registered Feedback Cycles support rherveille 7788d 23h /
42 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8121d 10h /
41 specs version 1.1 rherveille 8121d 10h /
40 no message rherveille 8121d 10h /
39 Changed video timing generator.
Changed wishbone master vertical gate count code.
Fixed a potential bug in the wishbone slave (cursor color register readout).		 rherveille 8121d 11h /
38 Changed testbench to reflect modified VGA timing generator. rherveille 8121d 11h /
37 Fixed a potential reset bug in the hint & vint generation. rherveille 8136d 15h /
36 Fixed two small bugs that only showed up when the hardware cursors were disabled rherveille 8144d 16h /
35 no message rherveille 8144d 19h /
34 Added hardware cursor support to wishbone master.
Added provision to turn-off 3D cursors.
Fixed some minor bugs.		 rherveille 8168d 05h /
33 Added 64x64pixels 4bpp hardware cursor support. rherveille 8168d 10h /
32 Fixed dat_o incomplete sensitivity list. rherveille 8175d 15h /
31 Some minor bug-fixes.
Changed vga_ssel into vga_curproc (cursor processor).		 rherveille 8184d 10h /
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8193d 15h /
29 Added wb_ack delay section to testbench rherveille 8193d 16h /
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8203d 17h /
27 Added 32bpp
Fixed some typos
Added bandwidth section		 rherveille 8203d 17h /
26 Added 32bpp tests rherveille 8203d 17h /
25 C-include file.
Initial release		 rherveille 8270d 11h /
24 Updated testbench for VGA/LCD Core version 2.0 rherveille 8277d 14h /
23 Added Copyright/Licence header rherveille 8278d 09h /

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