| Rev |
Log message |
Author |
Age |
Path |
| 88 |
Updated with complete code |
rehayes |
4780d 15h |
/ |
| 87 |
First pass JTAG TAP, state machine working but needs work to complete reset of TAP. |
rehayes |
4907d 05h |
/ |
| 86 |
Add JTAG test tasks |
rehayes |
4907d 06h |
/ |
| 85 |
Corrections to instruction set details example code, added test bench debugger. |
rehayes |
5181d 15h |
/ |
| 84 |
Added notes on SKIPJACK encrypt/decrypt applications, testbench debugger and user guide corrections. |
rehayes |
5181d 15h |
/ |
| 83 |
Add subroutine quailifier. |
rehayes |
5181d 15h |
/ |
| 82 |
Added debug module to assist in software debugging. |
rehayes |
5182d 09h |
/ |
| 81 |
Initial checkin of the SKIPJACK encrypt/decrypt application program |
rehayes |
5182d 10h |
/ |
| 80 |
Added IRQ bypass registers and Test bench appendix |
rehayes |
5244d 11h |
/ |
| 79 |
Added IRQ bypass registers and Test bench appendix |
rehayes |
5244d 11h |
/ |
| 78 |
Added IRQ bypass registers and Test bench appendix |
rehayes |
5244d 11h |
/ |
| 77 |
Documentation update |
rehayes |
5244d 11h |
/ |
| 76 |
Updated xgate_risc.v for xlink synthesis warnings. |
rehayes |
5267d 12h |
/ |
| 75 |
Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 |
rehayes |
5267d 12h |
/ |
| 74 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5272d 13h |
/ |
| 73 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5272d 13h |
/ |
| 72 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5272d 13h |
/ |
| 71 |
Added irq bypass registers to rtl, testbench and doc. |
rehayes |
5273d 15h |
/ |
| 70 |
Updated with interrupt bypass controll registers. |
rehayes |
5273d 16h |
/ |
| 69 |
New test to verify irq interrupt priority encoder. |
rehayes |
5273d 16h |
/ |
| 68 |
Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. |
rehayes |
5273d 16h |
/ |
| 67 |
Added irq bypass function and controll registers. Made lowest interrupt index highest priority. |
rehayes |
5273d 16h |
/ |
| 66 |
Fix testbench and RISC core related to debug mode and wait states. |
rehayes |
5293d 12h |
/ |
| 65 |
Parameterize delays based on number of RAM wait states. |
rehayes |
5293d 12h |
/ |
| 64 |
Fixed more bugs related to wait states and debug mode. |
rehayes |
5293d 12h |
/ |
| 63 |
Remove historical output ports that are no longer used. |
rehayes |
5303d 12h |
/ |
| 62 |
Cleanup implicit wire declarations. |
rehayes |
5303d 12h |
/ |
| 61 |
Update to RISC block to fix DEBUG mode, testbench update |
rehayes |
5310d 11h |
/ |
| 60 |
Add ability at insert wait states on RAM access |
rehayes |
5310d 12h |
/ |
| 59 |
Fix bug in entering DEBUG mode from WB bus command |
rehayes |
5310d 12h |
/ |
