| Rev |
Log message |
Author |
Age |
Path |
| 61 |
Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true. |
dgisselq |
3011d 09h |
/ |
| 60 |
LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively. |
dgisselq |
3011d 09h |
/ |
| 59 |
Simplified logic. |
dgisselq |
3011d 09h |
/ |
| 58 |
Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. |
dgisselq |
3011d 09h |
/ |
| 57 |
Fixed the TX/RX addresses so that they match the documentation: TX first, then
RX. |
dgisselq |
3019d 09h |
/ |
| 56 |
Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer. |
dgisselq |
3019d 09h |
/ |
| 55 |
Updated copyright notice. |
dgisselq |
3019d 09h |
/ |
| 54 |
Updated copyright notice. |
dgisselq |
3019d 09h |
/ |
| 53 |
Added a touch of error checking. |
dgisselq |
3059d 09h |
/ |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
3059d 09h |
/ |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
3069d 08h |
/ |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
3078d 10h |
/ |
| 49 |
Added some documentation to make the read and write calls easier to understand. |
dgisselq |
3087d 10h |
/ |
| 48 |
Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ... |
dgisselq |
3089d 12h |
/ |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
3089d 12h |
/ |
| 46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
3089d 12h |
/ |
| 45 |
Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference. |
dgisselq |
3093d 08h |
/ |
| 44 |
NELM parameter adjusted to reflect the maximum number of lines the compressed
scope can handle: 31, not 32. |
dgisselq |
3093d 08h |
/ |
| 43 |
Commentary changes only, no substance. |
dgisselq |
3093d 08h |
/ |
| 42 |
Minor changes. |
dgisselq |
3093d 08h |
/ |
| 41 |
Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier. |
dgisselq |
3093d 08h |
/ |
| 40 |
This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb. |
dgisselq |
3094d 19h |
/ |
| 39 |
An attempt at a bugfix. We'll see if this works any better downstream. |
dgisselq |
3096d 14h |
/ |
| 38 |
Updated to remove the build dependence upon ZipCPU. |
dgisselq |
3096d 18h |
/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3097d 12h |
/ |
| 36 |
A linker script, appropriate to the XuLA25-LX25 SoC. |
dgisselq |
3097d 14h |
/ |
| 35 |
Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils. |
dgisselq |
3097d 14h |
/ |
| 34 |
Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.) |
dgisselq |
3101d 09h |
/ |
| 33 |
Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip. |
dgisselq |
3101d 10h |
/ |
| 32 |
Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate. |
dgisselq |
3101d 11h |
/ |
