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127 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7506d 03h /.
126 run_sim.scr renamed to run_sim for VATS. mohor 7506d 03h /.
125 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7508d 00h /.
124 Display for VATS added. mohor 7508d 00h /.
123 All flipflops are reset. mohor 7508d 00h /.
122 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7511d 00h /.
121 Port signals are all set to zero after reset. mohor 7511d 00h /.
120 test stall_test added. mohor 7511d 03h /.
119 cpu_stall_o activated as soon as bp occurs. mohor 7511d 04h /.
118 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7513d 00h /.
117 Define name changed. mohor 7513d 00h /.
116 Data latching changed when testing WB. mohor 7513d 00h /.
115 More debug data added. mohor 7513d 04h /.
114 CRC generation iand verification in bench changed. mohor 7513d 05h /.
113 IDCODE test improved. mohor 7513d 06h /.
112 dbg_tb_defines.v not used. mohor 7514d 01h /.
111 Define tap_defines.v added to test bench. mohor 7514d 01h /.
110 Waiting for "ready" improved. mohor 7514d 02h /.
109 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7514d 07h /.
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7514d 07h /.
107 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7515d 05h /.
106 Sensitivity list updated. simons 7515d 05h /.
105 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7515d 20h /.
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7515d 20h /.
103 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7515d 20h /.
102 New version. mohor 7515d 20h /.
101 Almost finished. mohor 7515d 21h /.
100 *** empty log message *** mohor 7516d 23h /.
99 cpu registers added. mohor 7516d 23h /.
98 This commit was manufactured by cvs2svn to create tag 'new_debug'. 7518d 02h /.

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