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Rev Log message Author Age Path
31 Core is now a Multimaster I2C controller. rherveille 7903d 06h /.
30 Small code simplifications rherveille 7903d 06h /.
29 Core is now a Multimaster I2C controller rherveille 7903d 07h /.
28 *** empty log message *** rherveille 7929d 00h /.
27 Cleaned up code rherveille 7929d 00h /.
26 *** empty log message *** rherveille 7932d 08h /.
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7960d 04h /.
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7960d 04h /.
23 *** empty log message *** rherveille 8087d 10h /.
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8097d 15h /.
21 no message rherveille 8183d 16h /.
20 Added Appendix A rherveille 8183d 16h /.
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8187d 12h /.
18 no message rherveille 8214d 08h /.
17 C-include file.
Initial release		 rherveille 8302d 12h /.
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8314d 12h /.
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8319d 10h /.
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8319d 11h /.
13 Fixed some synthesis warnings. rherveille 8330d 15h /.
12 no message rherveille 8336d 06h /.
11 Changed RST_LVL define to parameter. rherveille 8339d 14h /.
10 Created new directory structure.
Added Verilog version.		 rherveille 8361d 10h /.
9 Created directory structure (documentation, vhdl, verilog) rherveille 8431d 05h /.
8 Created directory structure (documentation, vhdl, verilog) rherveille 8431d 05h /.
7 added some remarks, fixed some sensitivity lists rherveille 8500d 08h /.
6 fixed typo txt -> txr rherveille 8504d 12h /.
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8511d 10h /.
4 WISHBONE I2C Master Core: initial release rherveille 8563d 13h /.
3 This commit was manufactured by cvs2svn to create tag 'first'. 8625d 12h /.
2 initial release rherveille 8625d 12h /.

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