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[/] [.] - Rev 38

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Rev Log message Author Age Path
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7639d 23h /.
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7676d 15h /.
36 Fixed cmd_ack generation item (no bug). rherveille 7791d 16h /.
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7825d 06h /.
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7829d 04h /.
33 Fixed a bug in the Command Register declaration. rherveille 7851d 14h /.
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7861d 13h /.
31 Core is now a Multimaster I2C controller. rherveille 7865d 14h /.
30 Small code simplifications rherveille 7865d 14h /.
29 Core is now a Multimaster I2C controller rherveille 7865d 15h /.
28 *** empty log message *** rherveille 7891d 08h /.
27 Cleaned up code rherveille 7891d 08h /.
26 *** empty log message *** rherveille 7894d 16h /.
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7922d 12h /.
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7922d 12h /.
23 *** empty log message *** rherveille 8049d 18h /.
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8059d 23h /.
21 no message rherveille 8145d 23h /.
20 Added Appendix A rherveille 8145d 23h /.
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8149d 20h /.
18 no message rherveille 8176d 16h /.
17 C-include file.
Initial release		 rherveille 8264d 20h /.
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8276d 20h /.
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8281d 18h /.
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8281d 18h /.
13 Fixed some synthesis warnings. rherveille 8292d 22h /.
12 no message rherveille 8298d 14h /.
11 Changed RST_LVL define to parameter. rherveille 8301d 21h /.
10 Created new directory structure.
Added Verilog version.		 rherveille 8323d 18h /.
9 Created directory structure (documentation, vhdl, verilog) rherveille 8393d 13h /.

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